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How are such low op-amp input currents possible?
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How are such low op-amp input currents possible?
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$begingroup$
I understand that op-amps have low input currents; that's one of their defining characteristics. But looking at the datasheet for the LMC6001 (amusingly called an "Ultra, Ultra-Low Input Current Amplifier" because one ultra just wasn't enough), I have to wonder: how the <censored> do they get such low input currents‽
The LMC6001 claims a maximum input bias current at 25°C of 25 femtoamperes. With its rated input offset voltage of 10mV between the pins, that's equivalent to a 400 GΩ resistor between the inputs, which are two adjacent pins on an SOIC package.
And then if you look at comparators, it's even more impressive. Take for example the TLV7211, where the input impedance is on the order of 100 TΩ, while being in an even smaller SC-70 package. How is this not dominated by leakage currents through the PCB and packaging?
operational-amplifier comparator input-impedance leakage-current
asked 3 hours ago
HearthHearth
4,3171036
$endgroup$
add a comment |
$begingroup$
I understand that op-amps have low input currents; that's one of their defining characteristics. But looking at the datasheet for the LMC6001 (amusingly called an "Ultra, Ultra-Low Input Current Amplifier" because one ultra just wasn't enough), I have to wonder: how the <censored> do they get such low input currents‽
The LMC6001 claims a maximum input bias current at 25°C of 25 femtoamperes. With its rated input offset voltage of 10mV between the pins, that's equivalent to a 400 GΩ resistor between the inputs, which are two adjacent pins on an SOIC package.
And then if you look at comparators, it's even more impressive. Take for example the TLV7211, where the input impedance is on the order of 100 TΩ, while being in an even smaller SC-70 package. How is this not dominated by leakage currents through the PCB and packaging?
operational-amplifier comparator input-impedance leakage-current
asked 3 hours ago
HearthHearth
4,3171036
$endgroup$
$begingroup$
The high input impedance is because they use insulated gate FETs. And of course the leakage across the PCB will tend to dominate, that's why you have to put guard rings around the inputs or stand them off on PTFE insulated posts.
$endgroup$
– Jack Creasey
3 hours ago
$begingroup$
Do they use any special plastic for the packaging of these to reduce leakage across the package itself, or is that not enough of a problem even at this low current level?
$endgroup$
– Hearth
3 hours ago
$begingroup$
For ultra high impedance there may be ground or guard pins ether side of the inputs. For the LMC6001 read 10.1 in the datasheet.
$endgroup$
– Jack Creasey
2 hours ago
1
$begingroup$
If you look at Keithley's boards, you'll also see FR4 cutouts to reduce current paths. But to get really low input levels, I had to get the ICs in waffle packs from Hamamatsu and from Burr Brown without the epoxy packaging, and learn to wire bond myself (found someone local willing to help me out.) The epoxy packages are too leaky between pins, as you realized -- certain COTO relays actually leak less. (I couldn't afford guard rings, FR4, or epoxy and also had to stabilize the temperature, too.)
$endgroup$
– jonk
1 hour ago
add a comment |
$begingroup$
I understand that op-amps have low input currents; that's one of their defining characteristics. But looking at the datasheet for the LMC6001 (amusingly called an "Ultra, Ultra-Low Input Current Amplifier" because one ultra just wasn't enough), I have to wonder: how the <censored> do they get such low input currents‽
The LMC6001 claims a maximum input bias current at 25°C of 25 femtoamperes. With its rated input offset voltage of 10mV between the pins, that's equivalent to a 400 GΩ resistor between the inputs, which are two adjacent pins on an SOIC package.
And then if you look at comparators, it's even more impressive. Take for example the TLV7211, where the input impedance is on the order of 100 TΩ, while being in an even smaller SC-70 package. How is this not dominated by leakage currents through the PCB and packaging?
operational-amplifier comparator input-impedance leakage-current
asked 3 hours ago
HearthHearth
4,3171036
$endgroup$
I understand that op-amps have low input currents; that's one of their defining characteristics. But looking at the datasheet for the LMC6001 (amusingly called an "Ultra, Ultra-Low Input Current Amplifier" because one ultra just wasn't enough), I have to wonder: how the <censored> do they get such low input currents‽
The LMC6001 claims a maximum input bias current at 25°C of 25 femtoamperes. With its rated input offset voltage of 10mV between the pins, that's equivalent to a 400 GΩ resistor between the inputs, which are two adjacent pins on an SOIC package.
And then if you look at comparators, it's even more impressive. Take for example the TLV7211, where the input impedance is on the order of 100 TΩ, while being in an even smaller SC-70 package. How is this not dominated by leakage currents through the PCB and packaging?
operational-amplifier comparator input-impedance leakage-current
operational-amplifier comparator input-impedance leakage-current
asked 3 hours ago
HearthHearth
4,3171036
asked 3 hours ago
HearthHearth
4,3171036
asked 3 hours ago
HearthHearth
4,3171036
asked 3 hours ago
HearthHearth
4,3171036
asked 3 hours ago
HearthHearth
4,3171036
4,3171036
$begingroup$
The high input impedance is because they use insulated gate FETs. And of course the leakage across the PCB will tend to dominate, that's why you have to put guard rings around the inputs or stand them off on PTFE insulated posts.
$endgroup$
– Jack Creasey
3 hours ago
$begingroup$
Do they use any special plastic for the packaging of these to reduce leakage across the package itself, or is that not enough of a problem even at this low current level?
$endgroup$
– Hearth
3 hours ago
$begingroup$
For ultra high impedance there may be ground or guard pins ether side of the inputs. For the LMC6001 read 10.1 in the datasheet.
$endgroup$
– Jack Creasey
2 hours ago
1
$begingroup$
If you look at Keithley's boards, you'll also see FR4 cutouts to reduce current paths. But to get really low input levels, I had to get the ICs in waffle packs from Hamamatsu and from Burr Brown without the epoxy packaging, and learn to wire bond myself (found someone local willing to help me out.) The epoxy packages are too leaky between pins, as you realized -- certain COTO relays actually leak less. (I couldn't afford guard rings, FR4, or epoxy and also had to stabilize the temperature, too.)
$endgroup$
– jonk
1 hour ago
add a comment |
$begingroup$
The high input impedance is because they use insulated gate FETs. And of course the leakage across the PCB will tend to dominate, that's why you have to put guard rings around the inputs or stand them off on PTFE insulated posts.
$endgroup$
– Jack Creasey
3 hours ago
$begingroup$
Do they use any special plastic for the packaging of these to reduce leakage across the package itself, or is that not enough of a problem even at this low current level?
$endgroup$
– Hearth
3 hours ago
$begingroup$
For ultra high impedance there may be ground or guard pins ether side of the inputs. For the LMC6001 read 10.1 in the datasheet.
$endgroup$
– Jack Creasey
2 hours ago
1
$begingroup$
If you look at Keithley's boards, you'll also see FR4 cutouts to reduce current paths. But to get really low input levels, I had to get the ICs in waffle packs from Hamamatsu and from Burr Brown without the epoxy packaging, and learn to wire bond myself (found someone local willing to help me out.) The epoxy packages are too leaky between pins, as you realized -- certain COTO relays actually leak less. (I couldn't afford guard rings, FR4, or epoxy and also had to stabilize the temperature, too.)
$endgroup$
– jonk
1 hour ago
$begingroup$
The high input impedance is because they use insulated gate FETs. And of course the leakage across the PCB will tend to dominate, that's why you have to put guard rings around the inputs or stand them off on PTFE insulated posts.
$endgroup$
– Jack Creasey
3 hours ago
$begingroup$
The high input impedance is because they use insulated gate FETs. And of course the leakage across the PCB will tend to dominate, that's why you have to put guard rings around the inputs or stand them off on PTFE insulated posts.
$endgroup$
– Jack Creasey
3 hours ago
$begingroup$
Do they use any special plastic for the packaging of these to reduce leakage across the package itself, or is that not enough of a problem even at this low current level?
$endgroup$
– Hearth
3 hours ago
$begingroup$
Do they use any special plastic for the packaging of these to reduce leakage across the package itself, or is that not enough of a problem even at this low current level?
$endgroup$
– Hearth
3 hours ago
$begingroup$
For ultra high impedance there may be ground or guard pins ether side of the inputs. For the LMC6001 read 10.1 in the datasheet.
$endgroup$
– Jack Creasey
2 hours ago
$begingroup$
For ultra high impedance there may be ground or guard pins ether side of the inputs. For the LMC6001 read 10.1 in the datasheet.
$endgroup$
– Jack Creasey
2 hours ago
1
1
$begingroup$
If you look at Keithley's boards, you'll also see FR4 cutouts to reduce current paths. But to get really low input levels, I had to get the ICs in waffle packs from Hamamatsu and from Burr Brown without the epoxy packaging, and learn to wire bond myself (found someone local willing to help me out.) The epoxy packages are too leaky between pins, as you realized -- certain COTO relays actually leak less. (I couldn't afford guard rings, FR4, or epoxy and also had to stabilize the temperature, too.)
$endgroup$
– jonk
1 hour ago
$begingroup$
If you look at Keithley's boards, you'll also see FR4 cutouts to reduce current paths. But to get really low input levels, I had to get the ICs in waffle packs from Hamamatsu and from Burr Brown without the epoxy packaging, and learn to wire bond myself (found someone local willing to help me out.) The epoxy packages are too leaky between pins, as you realized -- certain COTO relays actually leak less. (I couldn't afford guard rings, FR4, or epoxy and also had to stabilize the temperature, too.)
$endgroup$
– jonk
1 hour ago
add a comment |
2 Answers
2
active
oldest
votes
$begingroup$
The input impedance can't be compared directly with the leakage current.
Input impedance is the change in input current with voltage. An input could have a 1uA bias current and 1G$Omega$ input resistance if the 1uA was very stable with input voltage.
They're MOSFETs and almost zero gate leakage is completely normal. Remember that you can store charge for 100 years in nonvolatile memory just with a bit of charge on a tiny gate capacitance. The more impressive achievement is providing any kind of gate protection within that leakage requirement. I suspect they may have some clever bootstrap circuit to minimize leakage. You can search for patents to see if they've disclosed anything relevant (it would be a National Semiconductor patent).
There are options to using FR4 PCBs, which are not perfect even when perfectly clean (and are easily contaminated by some fluxes to have relatively massive leakage). Here is a document which discusses some of the issues. I think Bob Pease also had some good tips and tricks for achieving low leakage. You can avoid a PCB entirely for the low leakage pin and use a PTFE (teflon) standoff, for example.
answered 2 hours ago
Spehro PefhanySpehro Pefhany
210k5160422
$endgroup$
1
$begingroup$
You're right about input impedance. I got some words mixed up, apparently; I'll edit the question to fix that when I'm more confident I can think straight.
$endgroup$
– Hearth
2 hours ago
add a comment |
$begingroup$
They get such low input currents by proper use of CMOS transistors. There is a compromise in speed. You will not find GHZ CMOS op-amps.
The PCB layout MUST include 2 options in design. Guard rails between the input pins prevent leakage currents from nearby supply rails from causing offsets and noise in the outputs. Option 2 means using Teflon in that part of the board, along with routing out narrow strips of board. The input pin, which may have a 100 megohm resistor at its input(s), now has no contact with adjacent PCB traces at all. Some Teflon post are used with a tinned wire in the center, for inputs in the 100M to gigaohm range.
Meters that measure picoamps and picovolts make use of such circuit topology, with Teflon being used for the most demanding requirements. A separate dust shield and conformal coating prevent dust and moisture from causing noise and/or offset errors.
answered 2 hours ago
Sparky256Sparky256
12.1k21637
$endgroup$
add a comment |
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2 Answers
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active
oldest
votes
2 Answers
2
active
oldest
votes
active
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votes
$begingroup$
The input impedance can't be compared directly with the leakage current.
Input impedance is the change in input current with voltage. An input could have a 1uA bias current and 1G$Omega$ input resistance if the 1uA was very stable with input voltage.
They're MOSFETs and almost zero gate leakage is completely normal. Remember that you can store charge for 100 years in nonvolatile memory just with a bit of charge on a tiny gate capacitance. The more impressive achievement is providing any kind of gate protection within that leakage requirement. I suspect they may have some clever bootstrap circuit to minimize leakage. You can search for patents to see if they've disclosed anything relevant (it would be a National Semiconductor patent).
There are options to using FR4 PCBs, which are not perfect even when perfectly clean (and are easily contaminated by some fluxes to have relatively massive leakage). Here is a document which discusses some of the issues. I think Bob Pease also had some good tips and tricks for achieving low leakage. You can avoid a PCB entirely for the low leakage pin and use a PTFE (teflon) standoff, for example.
answered 2 hours ago
Spehro PefhanySpehro Pefhany
210k5160422
$endgroup$
1
$begingroup$
You're right about input impedance. I got some words mixed up, apparently; I'll edit the question to fix that when I'm more confident I can think straight.
$endgroup$
– Hearth
2 hours ago
add a comment |
$begingroup$
The input impedance can't be compared directly with the leakage current.
Input impedance is the change in input current with voltage. An input could have a 1uA bias current and 1G$Omega$ input resistance if the 1uA was very stable with input voltage.
They're MOSFETs and almost zero gate leakage is completely normal. Remember that you can store charge for 100 years in nonvolatile memory just with a bit of charge on a tiny gate capacitance. The more impressive achievement is providing any kind of gate protection within that leakage requirement. I suspect they may have some clever bootstrap circuit to minimize leakage. You can search for patents to see if they've disclosed anything relevant (it would be a National Semiconductor patent).
There are options to using FR4 PCBs, which are not perfect even when perfectly clean (and are easily contaminated by some fluxes to have relatively massive leakage). Here is a document which discusses some of the issues. I think Bob Pease also had some good tips and tricks for achieving low leakage. You can avoid a PCB entirely for the low leakage pin and use a PTFE (teflon) standoff, for example.
answered 2 hours ago
Spehro PefhanySpehro Pefhany
210k5160422
$endgroup$
1
$begingroup$
You're right about input impedance. I got some words mixed up, apparently; I'll edit the question to fix that when I'm more confident I can think straight.
$endgroup$
– Hearth
2 hours ago
add a comment |
$begingroup$
The input impedance can't be compared directly with the leakage current.
Input impedance is the change in input current with voltage. An input could have a 1uA bias current and 1G$Omega$ input resistance if the 1uA was very stable with input voltage.
They're MOSFETs and almost zero gate leakage is completely normal. Remember that you can store charge for 100 years in nonvolatile memory just with a bit of charge on a tiny gate capacitance. The more impressive achievement is providing any kind of gate protection within that leakage requirement. I suspect they may have some clever bootstrap circuit to minimize leakage. You can search for patents to see if they've disclosed anything relevant (it would be a National Semiconductor patent).
There are options to using FR4 PCBs, which are not perfect even when perfectly clean (and are easily contaminated by some fluxes to have relatively massive leakage). Here is a document which discusses some of the issues. I think Bob Pease also had some good tips and tricks for achieving low leakage. You can avoid a PCB entirely for the low leakage pin and use a PTFE (teflon) standoff, for example.
answered 2 hours ago
Spehro PefhanySpehro Pefhany
210k5160422
$endgroup$
The input impedance can't be compared directly with the leakage current.
Input impedance is the change in input current with voltage. An input could have a 1uA bias current and 1G$Omega$ input resistance if the 1uA was very stable with input voltage.
They're MOSFETs and almost zero gate leakage is completely normal. Remember that you can store charge for 100 years in nonvolatile memory just with a bit of charge on a tiny gate capacitance. The more impressive achievement is providing any kind of gate protection within that leakage requirement. I suspect they may have some clever bootstrap circuit to minimize leakage. You can search for patents to see if they've disclosed anything relevant (it would be a National Semiconductor patent).
There are options to using FR4 PCBs, which are not perfect even when perfectly clean (and are easily contaminated by some fluxes to have relatively massive leakage). Here is a document which discusses some of the issues. I think Bob Pease also had some good tips and tricks for achieving low leakage. You can avoid a PCB entirely for the low leakage pin and use a PTFE (teflon) standoff, for example.
answered 2 hours ago
Spehro PefhanySpehro Pefhany
210k5160422
answered 2 hours ago
Spehro PefhanySpehro Pefhany
210k5160422
answered 2 hours ago
Spehro PefhanySpehro Pefhany
210k5160422
answered 2 hours ago
Spehro PefhanySpehro Pefhany
210k5160422
210k5160422
1
$begingroup$
You're right about input impedance. I got some words mixed up, apparently; I'll edit the question to fix that when I'm more confident I can think straight.
$endgroup$
– Hearth
2 hours ago
add a comment |
1
$begingroup$
You're right about input impedance. I got some words mixed up, apparently; I'll edit the question to fix that when I'm more confident I can think straight.
$endgroup$
– Hearth
2 hours ago
1
1
$begingroup$
You're right about input impedance. I got some words mixed up, apparently; I'll edit the question to fix that when I'm more confident I can think straight.
$endgroup$
– Hearth
2 hours ago
$begingroup$
You're right about input impedance. I got some words mixed up, apparently; I'll edit the question to fix that when I'm more confident I can think straight.
$endgroup$
– Hearth
2 hours ago
add a comment |
$begingroup$
They get such low input currents by proper use of CMOS transistors. There is a compromise in speed. You will not find GHZ CMOS op-amps.
The PCB layout MUST include 2 options in design. Guard rails between the input pins prevent leakage currents from nearby supply rails from causing offsets and noise in the outputs. Option 2 means using Teflon in that part of the board, along with routing out narrow strips of board. The input pin, which may have a 100 megohm resistor at its input(s), now has no contact with adjacent PCB traces at all. Some Teflon post are used with a tinned wire in the center, for inputs in the 100M to gigaohm range.
Meters that measure picoamps and picovolts make use of such circuit topology, with Teflon being used for the most demanding requirements. A separate dust shield and conformal coating prevent dust and moisture from causing noise and/or offset errors.
answered 2 hours ago
Sparky256Sparky256
12.1k21637
$endgroup$
add a comment |
$begingroup$
They get such low input currents by proper use of CMOS transistors. There is a compromise in speed. You will not find GHZ CMOS op-amps.
The PCB layout MUST include 2 options in design. Guard rails between the input pins prevent leakage currents from nearby supply rails from causing offsets and noise in the outputs. Option 2 means using Teflon in that part of the board, along with routing out narrow strips of board. The input pin, which may have a 100 megohm resistor at its input(s), now has no contact with adjacent PCB traces at all. Some Teflon post are used with a tinned wire in the center, for inputs in the 100M to gigaohm range.
Meters that measure picoamps and picovolts make use of such circuit topology, with Teflon being used for the most demanding requirements. A separate dust shield and conformal coating prevent dust and moisture from causing noise and/or offset errors.
answered 2 hours ago
Sparky256Sparky256
12.1k21637
$endgroup$
add a comment |
$begingroup$
They get such low input currents by proper use of CMOS transistors. There is a compromise in speed. You will not find GHZ CMOS op-amps.
The PCB layout MUST include 2 options in design. Guard rails between the input pins prevent leakage currents from nearby supply rails from causing offsets and noise in the outputs. Option 2 means using Teflon in that part of the board, along with routing out narrow strips of board. The input pin, which may have a 100 megohm resistor at its input(s), now has no contact with adjacent PCB traces at all. Some Teflon post are used with a tinned wire in the center, for inputs in the 100M to gigaohm range.
Meters that measure picoamps and picovolts make use of such circuit topology, with Teflon being used for the most demanding requirements. A separate dust shield and conformal coating prevent dust and moisture from causing noise and/or offset errors.
answered 2 hours ago
Sparky256Sparky256
12.1k21637
$endgroup$
They get such low input currents by proper use of CMOS transistors. There is a compromise in speed. You will not find GHZ CMOS op-amps.
The PCB layout MUST include 2 options in design. Guard rails between the input pins prevent leakage currents from nearby supply rails from causing offsets and noise in the outputs. Option 2 means using Teflon in that part of the board, along with routing out narrow strips of board. The input pin, which may have a 100 megohm resistor at its input(s), now has no contact with adjacent PCB traces at all. Some Teflon post are used with a tinned wire in the center, for inputs in the 100M to gigaohm range.
Meters that measure picoamps and picovolts make use of such circuit topology, with Teflon being used for the most demanding requirements. A separate dust shield and conformal coating prevent dust and moisture from causing noise and/or offset errors.
answered 2 hours ago
Sparky256Sparky256
12.1k21637
edited 2 hours ago
answered 2 hours ago
Sparky256Sparky256
12.1k21637
answered 2 hours ago
Sparky256Sparky256
12.1k21637
answered 2 hours ago
Sparky256Sparky256
12.1k21637
12.1k21637
add a comment |
add a comment |
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$begingroup$
The high input impedance is because they use insulated gate FETs. And of course the leakage across the PCB will tend to dominate, that's why you have to put guard rings around the inputs or stand them off on PTFE insulated posts.
$endgroup$
– Jack Creasey
3 hours ago
$begingroup$
Do they use any special plastic for the packaging of these to reduce leakage across the package itself, or is that not enough of a problem even at this low current level?
$endgroup$
– Hearth
3 hours ago
$begingroup$
For ultra high impedance there may be ground or guard pins ether side of the inputs. For the LMC6001 read 10.1 in the datasheet.
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– Jack Creasey
2 hours ago
1
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If you look at Keithley's boards, you'll also see FR4 cutouts to reduce current paths. But to get really low input levels, I had to get the ICs in waffle packs from Hamamatsu and from Burr Brown without the epoxy packaging, and learn to wire bond myself (found someone local willing to help me out.) The epoxy packages are too leaky between pins, as you realized -- certain COTO relays actually leak less. (I couldn't afford guard rings, FR4, or epoxy and also had to stabilize the temperature, too.)
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– jonk
1 hour ago